The present invention relates to the field of design simulation and verification; more particularly, the present invention relates to augmenting design descriptions to perform design verification by symbolic simulation.
The sophistication of modern integrated circuit (IC) design means that designers have to rely on automation tools (ICDA) to manage the complexity. Over the past two decades, new tools have continually been developed to increase the level of automation and enable designers to develop increasingly complex and powerful IC products.
The increasing demand for new IC design tools is fueled by rapidly changing IC fabrication process technology. As IC feature sizes shrink to dimensions of 0.25 micron and smaller, the complexity of the designs (number of devices on a single chip) drives the need for improved techniques to design and verify the required functionality.
The continuing increase in IC design complexity, along with the lack of specific automation tools, has led to design verification becoming a major design bottleneck.
There are a number of alternatives currently being used to reduce the verification bottleneck. These include both dynamic and static verification. Dynamic verification is the standard approach to verification. Recent advances in dynamic verification can be categorized into two categories: testbench management and augmented verification techniques.
Testbench management tools abstract the creation of test vectors to a higher level. These tools provide a language to help an individual create tests and measurement tools to help the individual quantify how good coverage is. Testbench management has a number of advantages that include providing an evolutionary step to the problem of design verification, automating many of the repetitive tasks and helps the designer focus on the problem of what to test, and providing a way of reducing the ambiguity of the test specification. Testbench management provides a number of disadvantages which include being based on the continued use of digital or binary simulation and large numbers of test vectors, forcing a designer to use a proprietary test language to express tests, and having non-simplified debugging.
Augmented verification techniques can be used with existing approaches and testbench management tools. Testbench management tools provide some augmented verification techniques, but these augmented techniques seek to improve measurement and increase test coverage. The use of augmented verification techniques is advantageous in that it provides an evolutionary step to the problem of design verification, improves the observability of the tests, and automates some of the steps of test creation to improve the scope of testing. The disadvantages of augmented verification techniques include being based on the use of binary simulation and large numbers of vectors, forcing a designer to use a proprietary methodology, and having no guarantee that the tests will catch all problems.
Static verification is a new technology that attempts to formally prove that a design meets its specifications.
Other verification techniques include equivalence checking which compares two gate level netlists is fairly established and its benefits are not an issue. However, application of the same formal techniques to compare RTL or behavior against a specification is still problematic. Model checking (behavior/RTLxe2x80x94RTL/gate checking) is still in the very early stages of use. Its inherent limitation of a maximum of about 200 registers means that model checking has very limited use without extensive engineering effort.
The advantages of this approach include providing exhaustive and conclusive proof that the design is correct, managing non-linear growth in design size, and providing rapid response and precise debugging. The disadvantages of this approach include having technical limitations such that it is only appropriate for a very small number of designs, very hard for engineers to grasp, and demands substantial reworking of design capture techniques.
Both dynamic and static approaches have merit; however, there is an immediate problem that neither approach can solve today. Until now, there has been no adequate solution to the growing crisis of design verification. Existing simulation techniques are not able to keep up with complexity growth. Formal techniques have too many restrictions and functional verification is the major cause of problems in a design project. Therefore, a need exists to provide an improved simulation technique that reduces the number of restrictions that currently exist in a design project.
A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first programming interface call and instructing a symbolic simulator with the first programming interface call to treat the at least one object as a symbol.